This was my Senior design project at Carnegie Mellon, a phased array of microphones which I called “Sonicam”. This blog was largely taken from the project logs submitted as part of the class. I chose this project almost entirely as an excuse to mess around with phased arrays, which is something I’ve wanted to do […]
Introduction and Project Summary Read More »
This was the final presentation given for the class, and will be the last post on the project blog.
This week I mainly finished the hardware and continued refining the real-time imaging. The hardware was half completed at the beginning of this week, with 48 microphones assembled on their boards and tested. At the beginning of this week I assembled the remaining 48. Since the package for these microphones, LGA_CAV, are very small, with
Jonathan’s Status Update for Saturday April 25 Read More »
This week saw the completion of all major parts of the project. The hardware is finished: And software is working: John worked mainly on finishing the hardware, completing the remaining half of the array this week, Sarah and Ryan on the software, generating images from array data. Going forward, we mainly plan to make minor
Team status update for Saturday April 25 Read More »
This week we made significant headway towards the finished project. The first three microphone boards are populated and tested, and most of the software for real-time visualization and beamforming has been written. At this point, we all have our heads down, finishing our portion of the project, so most of the progress this week has
Team status report for Saturday April 18 Read More »
This week I mainly worked on improving the real-time visualizer, and building more of the hardware. The real-time visualizer previously just did time-domain delay and sum, followed by a Fourier transform of the resulting data. This worked but is slow, particularly as more pixels are added to the output image. To improve the resolution and
Jonathan’s status report for Saturday, Apr. 18 Read More »
This week started with the midpoint demo, which worked relatively well, showing mainly the real-time visualization shown in one of the previous updates. During the remainder of the week significant progress was made in several areas, particularly the network driver, which was previously impeding progress on the processing software. Some progress on the hardware was
Team status report for Saturday April 11 Read More »
This week I mainly worked on the network driver and microphone board hardware. Last week, there was a problem that emerged with the network driver dropping up to 30% of the packets being transmitted from the FPGA, I spent most of this week working on resolving that. The library being used previously was the “hypermedia.net”
Jonathan’s Status Report for Saturday, Apr. 11 Read More »
This week significant progress made in all areas of the project, including the hardware/FPGA component catching back up to the planned timeline. To prepare for the midpoint demo on Monday, all group members have been working on getting some part of their portion of the project to the point where it can be demonstrated. John
Team Status Update for Saturday, Apr. 4 Read More »
This week I mainly worked on updating the FPGA firmware and computer network driver. Boards arrived yesterday, but I haven’t had time to begin populating them. Last week, the final components of the network driver for the FPGA were completed, this week I was able to get microphone data from a pair of microphones back
Jonathan’s Status Report for Saturday, Apr. 4 Read More »
This week I mainly worked on the microphone boards and FPGA drivers. The microphone boards were finished early this week, and ordered on Wednesday. They were fabricated and shipped yesterday, and expected to arrive by next Friday (4/3). As mentioned previously, this design uses a small number of large boards with 16 microphones each, connected
Jonathan’s Status Report for Saturday, Mar. 28 Read More »
This week largely saw a return to a more normal work schedule, and beginning to act on the updated plan. Our new timeline to account for the recent changes is shown below: Most components are on track or completed, though there are several components which have fallen slightly behind. Mainly the computer-side driver to receive
Team Status Update for Saturday, Mar. 28 Read More »
All of the changes to daily life this week didn’t leave much time for work on capstone outside of class, so the additional work completed has been minimal. Most of what I was able to work on this week was design of the microphone array boards, which was originally scheduled to be finished over the
Jonathan’s Status Report for Saturday, Mar. 21 Read More »
This week brought some significant changes to the project, the new scope is summarized in our updated SOW: Team E0 Statement of Work_3_21_20 Short summary is that the only major changes are to the details of the design, to account for losing access to campus resources, and several tests/characterizations/calibrations of the array will no longer
Team Status Update for Saturday, Mar. 21 Read More »
Unsurprisingly there were some significant changes to the progression of the project this week. Before the switch to online classes was announced, I completed two things for this project, pertaining to the aspect which was slightly behind schedule, the gigabit ethernet. The Numato PHY was ordered last week, but had not come in by Wednesday,
Jonathan’s Status Report for Saturday, Mar. 14 Read More »
This week I mainly worked on the design report, and debugging ethernet. After CDR we had a few comments, one of which was concerning the choice of FPGA. Based on that, I went through and evaluated whether we should switch up to a newer/larger FPGA. I did some preliminary checks on the expected size of
Jonathan’s Status Update for Saturday, Feb. 29 Read More »
We’re continuing our investigation with implementing 1Gbps Ethernet with our FPGA. The Spartan 6 board does come with two Gigabit Ethernet ports, but since it’s not a development board (actually an LED array controller), the Broadcom transceiver does not have a public datasheet for it, so it’s hard to control, even though it’s using the
Team Status Update for Saturday, Feb. 29 Read More »
This week I mainly worked on getting the gigabit ethernet interface working on a development board, and, put together a board for testing the PDM microphones. After getting the FPGA toolchain set up last week, I spent most of this week putting together a basic RGMII interface. A significant amount of the time spent was
Jonathan’s Status Update for 2/22 Read More »
Currently the primary risks are: Not being able to get the gigabit ethernet working. Managing this mainly by addressing it first,as it’s likely to be one of the most challenging parts of the project. If we’re unable to get it working, it’s best to know soon so we can switch to another interface as soon
Team Status Update for Saturday, Feb. 22 Read More »
What did you personally accomplish this week on the project? Give files or photos This week I mainly did simulations of different array geometries, microphone quantities, and spatial distributions. More of these images are in the team report, but a specific result of note is shown below: This was a simulation of a single point
Status Update for 2/15 Read More »
We have the results of several simulations of different array geometries, sizes, and frequencies of interest. In all cases, they are attempting to image a scene with a single source at a specific frequency. Plots are 4 separate images of the same scene, at different frequencies, but keeping all other parameters the same. The frequency
Team Status Update for Saturday, Feb. 15 Read More »