This week I mainly worked on the design report, and debugging ethernet.
After CDR we had a few comments, one of which was concerning the choice of FPGA. Based on that, I went through and evaluated whether we should switch up to a newer/larger FPGA. I did some preliminary checks on the expected size of the final design, as was suggested during CDR. Since there is very little processing done on the FPGA, it is mostly just used for data acquisition, the required logic took around 30% of the space available, even with an intentionally inefficient PDM filter.
This used some stand-in logic for the microphone acquisition and filtering, but should take similar space to the final filter.
I also worked some with Ryan on the PDM microphones, we were able to get some very basic data off of a microphone (in this case, given an 820Hz sine wave):
One minor change to the plan is that we plan to buy the Numato PHY this coming week, as the GbE development is falling behind. Other than that, we are still on track. In the mean time, I will also begin using a simple USB 2.0 interface for the FPGA based on a teensy 4.0, as a stop-gap while working on GbE.