status report

Jonathan’s Status Update for Saturday April 25

This week I mainly finished the hardware and continued refining the real-time imaging. The hardware was half completed at the beginning of this week, with 48 microphones assembled on their boards and tested.  At the beginning of this week I assembled the remaining 48. Since the package for these microphones, LGA_CAV, are very small, with […]

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Jonathan’s Status Report for Saturday, Apr. 11

This week I mainly worked on the network driver and microphone board hardware. Last week, there was a problem that emerged with the network driver dropping up to 30% of the packets being transmitted from the FPGA, I spent most of this week working on resolving that.  The library being used previously was the “hypermedia.net”

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Jonathan’s Status Report for Saturday, Apr. 4

This week I mainly worked on updating the FPGA firmware and computer network driver.  Boards arrived yesterday, but I haven’t had time to begin populating them. Last week, the final components of the network driver for the FPGA were completed, this week I was able to get microphone data from a pair of microphones back

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Jonathan’s Status Report for Saturday, Mar. 28

This week I mainly worked on the microphone boards and FPGA drivers.  The microphone boards were finished early this week, and ordered on Wednesday.  They were fabricated and shipped yesterday, and expected to arrive by next Friday (4/3). As mentioned previously, this design uses a small number of large boards with 16 microphones each, connected

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Team Status Update for Saturday, Mar. 21

This week brought some significant changes to the project, the new scope is summarized in our updated SOW: Team E0 Statement of Work_3_21_20 Short summary is that the only major changes are to the details of the design, to account for losing access to campus resources, and several tests/characterizations/calibrations of the array will no longer

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Jonathan’s Status Report for Saturday, Mar. 14

Unsurprisingly there were some significant changes to the progression of the project this week.  Before the switch to online classes was announced, I completed two things for this project, pertaining to the aspect which was slightly behind schedule, the gigabit ethernet. The Numato PHY was ordered last week, but had not come in by Wednesday,

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Jonathan’s Status Update for Saturday, Feb. 29

This week I mainly worked on the design report, and debugging ethernet. After CDR we had a few comments, one of which was concerning the choice of FPGA.  Based on that, I went through and evaluated whether we should switch up to a newer/larger FPGA.  I did some preliminary checks on the expected size of

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