Jonathan’s Status Report

This week I mainly finished the hardware and continued refining the real-time imaging. The hardware was half completed at the beginning of this week, with 48 microphones assembled on their boards and tested.  At the beginning of this week I assembled the remaining 48. Since the package for these microphones, LGA_CAV, are very small, with […]

This week I mainly worked on the network driver and microphone board hardware. Last week, there was a problem that emerged with the network driver dropping up to 30% of the packets being transmitted from the FPGA, I spent most of this week working on resolving that.  The library being used previously was the “hypermedia.net”

This week I mainly worked on updating the FPGA firmware and computer network driver.  Boards arrived yesterday, but I haven’t had time to begin populating them. Last week, the final components of the network driver for the FPGA were completed, this week I was able to get microphone data from a pair of microphones back

This week I mainly worked on the microphone boards and FPGA drivers.  The microphone boards were finished early this week, and ordered on Wednesday.  They were fabricated and shipped yesterday, and expected to arrive by next Friday (4/3). As mentioned previously, this design uses a small number of large boards with 16 microphones each, connected

All of the changes to daily life this week didn’t leave much time for work on capstone outside of class, so the additional work completed has been minimal. Most of what I was able to work on this week was design of the microphone array boards, which was originally scheduled to be finished over the

Unsurprisingly there were some significant changes to the progression of the project this week.  Before the switch to online classes was announced, I completed two things for this project, pertaining to the aspect which was slightly behind schedule, the gigabit ethernet. The Numato PHY was ordered last week, but had not come in by Wednesday,

This week I mainly worked on the design report, and debugging ethernet. After CDR we had a few comments, one of which was concerning the choice of FPGA.  Based on that, I went through and evaluated whether we should switch up to a newer/larger FPGA.  I did some preliminary checks on the expected size of

This week I mainly worked on getting the gigabit ethernet interface working on a development board, and, put together a board for testing the PDM microphones. After getting the FPGA toolchain set up last week, I spent most of this week putting together a basic RGMII interface.  A significant amount of the time spent was