NASA Robotic Mining Competition
Iowa State University - 2016, 2017
Designed, built, and tested control electronics for the twin robots entered in the 2016 and 2017 NASA RMC by Iowa State.
- Zynq based system, using Microzed SOM
- White box on left side of the rear of the robot
- Power management system: Smart Management Of Robot Energy (S.M.O.R.E.)
- Monitors and controls power for all motors, sensors, and the Microzed
- Supercapacitor backup to allow graceful shutdown when power is cut
- Black, brown and white box on the right side of the robot
- Control functions divided between Raspberry pi, Mojo FPGA, and teensy 3.2
- Designed, ordered, assembled, programmed, and tested in less than one month
MIT Lincoln Laboratory - 2018
Colibri started as an Intern Innovative Idea Challenge (I3C) project between another intern, Peter Sharpe and I. It is a new type of multirotor that uses a single, large rotor for most of its lift, and three additional fixed rotors for control. The initial proof of concept was designed to demonstrate the layout and control system, and secure funding. The second prototype was built to demonstrate the feasibility of using a gas engine to directly power the main rotor.
- 20″ main rotor
- 285 KV main motor
- 6S, 2200mAh battery
- 140W hover power
- 48″ main rotor
- 1.2 HP 2 stroke engine
- 6S, 1000mAh battery
Senior Design Project
Carnegie Mellon University - 2020
A phased array of digital microphones connected to an FPGA – capable of performing beamforming for acoustic imaging and basic sonar.
- 96 PDM digital microphones in an 8 * 12 grid
- Xilinx Spartan-6 FPGA with Gigabit Ethernet PHY to upload data to a computer
- Real-time and post-processed visualizations implemented
The MacroProcessor - 2014
This was a processor composed of discreet, 74-series logic chips and assembled on a wire wrap board. I designed and built this in High School as a way to learn about digital logic, processor design, and assembly programming. When starting, I had no experience with any of these, but was able to learn them together during the course of this project. The end result was not particularly useful or capable, since it’s purpose was entirely self-educational. In 2015, I ported the design to Verilog and got it running on an FPGA, as well.
- Clock speeds reaching up to 100KHz
- 7 instructions
- One program count register, two general purpose registers, two output registers
- 128 bytes of working memory
- 8 bit architecture